SCQF Level 7


  • Engineering

Why take this course?

Much of the developments seen today in modern technology are down to the techniques you will study in this unit – computers, internet technology (switches hubs and routers), CD and DVD technology, mini disks, MP3 players, electronic musical instruments, MIDI, MP3 players, mobile phones, satellite communications, CAD/CAM systems – the list goes on.

This Unit was developed for the HNC and HND Electronics Group Awards, but may also be taken as a stand alone HN Unit. Its purpose is to provide you with the necessary knowledge to understand the organisation of sequential logic devices and circuits, and to develop skills to design, simulate, build and test sequential logic circuits.

Credit points and level: 1 HN credit at SCQF level 7: (8 SCQF credit points at SCQF level 7).

What you will experience

You will learn how Sequential Logic Circuits are organised, how they are different from combinational logic circuits and also how they are constructed using a mixture of gates and bistables. When you studied combinational logic you learned about the basic building block of a combinational logic circuit – the gate; in this unit you will learn about the basic building block of a sequential logic circuit – the bistable. You will investigate the operation of the most common bistables and how they can be connected to form sequential logic circuits, and also learn how to design the two major classes of sequential circuit – the sequence generator and the sequence detector (these circuits are at the heart of all of the technologies mentioned above).

In modern electronic design, computers are used to simulate designs before going to the expense of production. This Unit will teach you how to simulate your designs on computer, and allow you to develop practical skills that will enable you to successfully build and test the designs you have created.

You will be required to undertake both written graphical, computer simulation and practical assessments. The assessment for outcomes 1, 2 and the shift register block diagrams part of outcome 3 are combined into one assessment paper. This paper should be taken by candidates at one single assessment event, lasting one hour. The assessment paper should be composed of a suitable balance of short answer, restricted response and written graphical exercises as specified for each outcome. Assessment should be conducted under controlled, supervised conditions.

The design part of outcome 3 should be carried out under closed book conditions followed by the simulation, build and test assessment for outcome 4, carried out as an assignment. The design, simulate, build and test should be done within 3 hours. It should be noted that candidates must achieve all the minimum evidence specified for each outcome in order to pass the unit.